california micro devices pac dn004 diode forward dc current (note 1) 20ma storage temperature -65 c to 150 c operating temperature range -20c to 85c dc voltage at any channel input v n -0.5v to v p +0.5v note 1: only one diode conducting at a time. 2 channel esd protection array features ? 2-channel esd protection ? 15kv esd protection (hbm) ? 8kv contact discharge esd protection per iec 61000-4-2 ? low loading capacitance, 3 pf typ. ? miniature 4-pin sot-143 package product description the pac? dn004 is a diode array designed to provide two channels of esd protection for electronic components or sub- systems. each channel consists of a pair of diodes which steers the esd current pulse either to the positive (v p ) or negative (v n ) supply. the pac? dn004 will protect against esd pulses up to 15 kv human body model, and 8kv contact discharge per international standard iec 61000-4-2. this device has identical characteristics as the pac? dn006 (6 channel array). they can be used together in order to provide a larger number of protected inputs if required. this device is particularly well-suited for portable electronics (e.g. cellul ar phones, pdas, notebook computers) because of its small package footprint, high esd protection level, and low loading capacitance. it is also suitable for protecting video output lines and i/o ports in computers and peripheral equipment. applications ? i/o port: protection for cellular phones, notebooks computers, pda, etc. ? esd protection for sensitive electronic equipment. ? esd protection for applications where low capacitive loading is required. 1 c0280498d note 2: from i/o pins to v p or v n only. v p bypassed to v n with 0.2 f ceramic capacitor. note 3: human body model per mil-std-883, method 3015, c discharge =100pf, r discharge =1.5k w , v p =5.0v, v n =gnd. note 4: this parameter is guaranteed by characterization. note 5: standard iec 61000-4-2 with c discharge =150pf, and r discharge =330 w , v p =5v, v n =gnd. 1 i/o 1 i/o 2 v v n p 3 2 4 11/99 ?1999 california micro devices corp. all rights reserved. p/active ? is a registered trademark and pac is a trademark of california micro devices. 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com s g n i t a r m u m i x a m e t u l o s b a n o i t a r u g i f n o c c i t a m e h c s s n o i t a c i f i c e p s d r a d n a t s r e t e m a r a p . n i m. p y t. x a m e g a t l o v y l p p u s g n i t a r e p ov ( p v - n ) v 5 . 5 v ( , t n e r r u c y l p p u s p v - n c 5 2 = t , v 5 . 5 = ) a 0 1 , e g a t l o v d r a w r o f e d o i di f c 5 2 = t , a m 0 2 =v 5 6 . 0v 5 9 . 0 n o i t c e t o r p d s e m e t s y s - n i , t u p n i l e n n a h c y n a t a e g a t l o v e g r a h c s i d k a e p ) 2 e t o n ( 0 0 0 5 1 0 3 d o h t e m , l e d o m y d o b n a m u h ) 4 , 3 e t o n ( v k 5 1 0 0 0 2 - 4 - 0 0 0 1 6 c e i r e p e g r a h c s i d t c a t n o c e t o n ( 5 ) v k 8 c 5 2 = t , m b h d s e v k 5 1 @ e g a t l o v p m a l c l e n n a h c ) 4 , 3 s e t o n ( 0 0 0 s t n e i s n a r t e v i t i s o p 0 0 0 s t n e i s n a r t e v i t a g e n v p v 0 . 3 1 + v n v 0 . 3 1 - c 5 2 = t , t n e r r u c e g a k a e l l e n n a h c a 1 . 0 a 0 . 1 ) z h m 1 @ d e r u s a e m ( e c n a t i c a p a c t u p n i l e n n a h c v p v , v 5 = n , v 0 =v n i v 5 . 2 = ) 4 e t o n ( f p 3f p 6 g n i t a r r e w o p e g a k c a p w m 5 2 2
california micro devices pac dn004 t s r a d n a n o i t a m r o f n i g n i r e d r o t r a p d e g a k c a pr e b m u n t r a p g n i r e d r o s n i pe l y t sg n i k r a m t r a p 43 4 1 - t o s4 0 0 n d ?1999 california micro devices corp. all rights reserved. 11/99 2 input capacitance vs. input voltage 0 1 2 3 4 5 012345 input voltage input capacitance (pf ) typical variation of c in with v in (v p = 5v, v n = 0v, 0.1 m f chip capacitor between v p & v n ) 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com when placing an order please specify desired shipping: tubes or tape & reel. application information see also california micro devices application note ap209, ?design considerations for esd protection.? in order to realize the maximum protection against esd pulses, care must be taken in the pcb layout to minimize parasitic series inductances to the supply and ground rails. refer to figure 1, which illustrates the case of a positive esd pulse applied between an input channel and chassis ground. the parasitic series inductance back to the power supply is represented by l 1 . the voltage v z on the line being protected is: v z = forward voltage drop of d 1 + l 1 x d(i esd )/dt + v supply where i esd is the esd current pulse, and v supply is the positive supply voltage. an esd current pulse can rise from zero to its peak value in a very short time. as an example, a level 4 contact discharge per the iec 61000-4-2 standard results in a current pulse that rises from zero to 30 amps in 1ns. here d(i esd )/dt can be approximated by d i esd / d t, or 30/(1x10 -9 ). so just 10nh of series inductance (l 1 ) will lead to a 300v increment in v z ! figure 1
california micro devices pac dn004 similarly for negative esd pulses, parasitic series inductance from the v n pin to the ground rail will lead to drastically increased negative voltage on the line being protected. another consideration is the output impedance of the power supply for fast transient currents. most power supplies exhibit a much higher output impedance to fast transient current spikes. in the v z equation above, the v supply term, in reality, is given by (v dc + i esd x r out ), where v dc and r out are the nominal supply dc output voltage and effective output impedance of the power supply respectively. as an example, a r out of 1 ohm would result in a 10v increment in v z for a peak i esd of 10a. to mitigate these effects, a high frequency bypass capacitor should be connected between the v p pin of the esd protection array and the ground plane. the value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the esd pulse with minimal change in v p . typically a value in the 0.1 f to 0.2 f range is adequate for iec-61000-4-2 level 4 contact discharge protection (8kv). for higher esd voltages, the bypass capacitor should be increased accordingly. ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. electrolytic capacitors should be avoided as they have poor high frequency characteristics. for extra protection , connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. the breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. as a general rule, the esd protection array should be located as close as possible to the point of entry of expected electrostatic discharges. the power supply bypass capacitor mentioned above should be as close to the v p pin of the protection array as possible, with minimum pcb trace lengths to the power supply and ground planes to minimize stray series inductance. 3 11/99 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com ?1999 california micro devices corp. all rights reserved.
|
